I2C BUS

I2C BUS Electronic Design & Firmware by Embedded Design Engineer John Heritage

 

I2C BUS (Inter Integrated Circuit)

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I2The Inter-Integrated Circuit bus (I2C) is a patented interface developed by Philips Semiconductors. (In order for an IC manufacturer to implement the I2C bus in hardware, they must obtain licensing from Philips.)

As a professional electronics design engineer, I very often choose different associated peripheral IC’s that use the I2C protocol, ADCs, DACs, LED Driver, EEprom, RTC, etc. This is a very widely used communication protocol allowing many devices to accessed on one 2 wire communications bus.

The I2C bus is a half-duplex, synchronous, multi-master bus requiring only two signal wires: data (SDA) and clock (SCL). These lines are pulled high via pull-up resistors and controlled by the hardware via open-drain drivers, giving a wired-AND interface.

I2C uses an addressable communications protocol that allows the master to communicate with individual slaves using a 7-bit or 10-bit address. Each device has an address that is assigned by Philips to the manufacturer of the device. In addition, several special addresses exist, including a “general call” address (which addresses every device on the bus) and a high-speed initiation address.

During communication with slave devices, the master generates all clock signals for both communication to and from the slave. Each communication begins with the master generating a start condition, an 8-bit data word, an acknowledge bit, followed by a stop condition or a repeated start. Each data bit transition takes place while SCL is low, except for the start and stop conditions. The start condition is a high-to-low transition of the SDA line while the SCL line is high. A stop condition is a low-to-high transition of the SDA line while the SCL line is high (see Figure 2). The acknowledge bit is generated by the receiver of the message by pulling the SDA line low while the master releases the line and allows it to float high. If the master reads the acknowledge bit as high, it should consider the last communication word not received and take appropriate action, including possibly resending the data.

I2C has a rather interesting feature called clock stretching, which is done when the slave device is unable to process the bit and wishes for more time. When this happens, the slave pulls the SCL line low. Since the signal behaves as a wired-AND, when the master releases the SCL line while the slave is “stretching” the clock, the master should notice that the line stays low. Upon seeing this, the master waits until the slave has processed the data bit and released the line. Once released by the slave, the SCL line floats back high, signaling to the master to send the next data bit..

The I2C bus has three speeds: slow (under 100Kbps), fast (400Kbps), and high-speed (3.4Mbps), each downward compatible. Philips has specified a recommended wiring arrangement should the signals need to leave the circuit board.

I2C bus distances are often limited to on-board communications, although I have heard of developers using I2C successfully over distances of 50 feet! The true limit to I2C distances is the bit-rate and capacitance of the bus. As such, for off-board communications, I2C is practically limited to under 10 feet for moderate speeds.

I2C Bus